1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the relationship between the design tolerances of an integrated circuit and the errors which arise on integrated circuits. This application claims the benefits of Provisional Application 60/658,179 filed on Mar. 4, 2005.
2. Description of the Prior Art
A significant problem in nanometre circuit design is achieving robust operation in the face of silicon variation, various noise sensitivities, simulation uncertainties and the like. The way designers deal with such problems is by adding enough design margin on critical parameters (such as operating voltage, device width, etc) to make sure that devices continue to operate correctly in the face of even worst case corner conditions. Margining is done throughout the entire design chain, e.g. process technology designers provide rules that are sufficiently padded so that circuit designers do not need to understand all the low level detail of the process. As a result, circuit libraries are padded simply to simplify their use by chip designers. Such margining continues at all levels of the design hierarchy.
The use of design margins in this way is an important tool to help abstract the detail between the implementation layers, but it comes with a significant efficiency cost: the penalties for ensuring that a chip works under all conditions are incurred even when the operating conditions are significantly better than worst case. Worst-case corner conditions are rare, especially the concurrent occurrence of all the issues that all the different design margins address.
A previously proposed technique described in WO-A-2004/08092 and in “Making Typical Silicon Matter with Razor” by Todd Austin et al IEEE Computer Society March 2004 (referred to herein as Razor) aims to recover some of the design-time efficiency loss due to margining by, at run-time, adapting the specific operating conditions on each individual integrated circuit to find the point at which errors occur and then use the detection and correction of such errors in a feedback control of the operating parameter concerned so as to run at a finite non-zero error rate right at the edge of what is possible for that individual integrated circuit.